Integrated circuits include multiple input/output (IO) pads that are used to convey signals to the integrated circuit and from the integrated circuit. Some IO pad circuits are used only to receive signals, other IO pad circuits are used to output signals and some IO pad circuits are used to receive signals and to output signals.
Usually, the number of signals that should be exchanged between the integrated circuit and its environment well exceeds the number of IO pad circuits, thus time division multiplexing is applied.
IO pads are required to change their characteristics (such as impedance, drive strength, slew rate and the like) in response to the functions that they are currently executing. In order to support these relatively rapid IO characteristic changes configurable IO pad circuits were developed.
Usually, a configurable IO pad circuit includes a control/configuration circuit and an IO pad. For simplicity of explanation the control/configuration circuits are referred to as control circuits.
The number of IO pad circuit configuration control signals is relatively large and can exceed ten. Multiple IO pad circuit configuration control signals form a multi-bit IO pad circuit configuration control word.
These signals are usually routed in dedicated IO channels that are relatively area-consuming and their design is relatively time consuming and complex. In a typical base-band integrated circuit the IO channels can require a total area of about two square millimeters.
FIG. 1 illustrates a lower part of an integrated circuit 5. IO pad circuits 6 surround IO channels 7 that in turn surround a portion 8 of the integrated circuit 5 that is not physically connected to the integrated circuit environment. Portion 8 can include one or more transistor based component such as but not limited to processors, memory units, logic and the like.
A more detailed illustration of configurable IO pad circuits and methods for configuring IO pad circuits are also illustrated in U.S. Pat. No. 6,851,079 of Hergott titled “JTAG test access port controller used to control input/output pad functionality”, and U.S. patent application serial number 2004/0117698 of Tran et al., titled “Programmable management IO pads for an integrated circuit”, which are incorporated herein by reference.
FIG. 2 illustrates a prior art integrated circuit 9 that includes IO pad circuits. An IO pad circuit includes an IO pad (POUT) 28 and an IO pad control circuit (PCNT) 29 that can receive information from JTAG compliant boundary scan cells. A PCNT 29 receives IO pad circuit configuration signals (denoted “control”) from core 11. The IO pad circuit configuration signals are routed vian IO channels, such as IO channels 7 of FIG. 1.
JTAG (also known as IEEE standard 1149.1) was designed in order to test integrated circuits. The IEEE standard 1149.1 defines a test access port (TAP) that may be used to access internal components of an integrated circuit. The TAP includes a boundary scan register 30, a one-bit long bypass register 12, an instruction register 18, a TAP controller 20, and an optional user defined data register 14.
A TAP receives various signals including a clock signal TCK, a test data input signal TDI, a test mode select signal TMS. The TAP can output a test data output signal TDO. Various control signals provided by the TAP controller 20, especially in response to TMS signals, select a path between the TDI and TDO ports of the TAP.
The instruction register 18 forms an instruction path while each of the boundary scan register 30, bypass register 12 and the optional user defined data register 14 defines a data path. Each data path and instruction path can be regarded as an internal test path of the TAP.
The TAP controller 20 is a state machine that can apply many stages, including various IEEE standard 1149.1 mandatory states. These mandatory states are controlled by the TMS signal. FIG. 4 illustrates the multiple states of the TAP controller 20: Test logic reset 40, run-test/idle 41, select DR scan 42, capture DR 43, shift DR 44, exit1 DR 45, pause DR 46, exit2 DR 47, update DR 48, select IR scan 52, capture IR 53, shift IR 54, exit1 IR 55, pause IR 56, exit2 IR 57 and update IR 58. The stages are illustrates as boxes that are linked to each other by arrows. The arrows are accompanied by digits (either 0 or 1) that illustrate the value of the TMS signal. These stages are well known in the art and require no further explanation.
Generally, the TAP controller 20 sends control signals that allow to input information into selected data and instruction paths, to retrieve information from said paths and to serially propagate (shift) information along data and instruction paths.
The boundary scan register 30 includes multiple boundary scan cells (denoted BSC) 32. Some BSCs are connected to input pad circuits 26 while others are connected, via PCNTs 29 to IO pad 28. Especially, each IO pad 28 is connected to a PCNT 29 that can receive configuration signals (denoted “control”) from core 11, data from certain BSCs and enable signals from other BSCs 32. A pair of BSCs are allocated for each IO pad 28.
FIG. 3 illustrates a prior art integrated circuit 9′ that includes IO pads 28, a TAP and a control selection multiplexer 23. For simplicity of explanation some registers were omitted.
Integrated circuit 9′ differs from integrated circuit 9 by including a control selection multiplexer 23 that can send to PCNTs 29 either (i) IO pad circuit configuration signals provided by core 11 or (ii) configuration signals generated by the TAP. The latter is usually provided during test mode while the former is provided during normal mode. A PCNT 29 can receive enable signals from one BSC, a data signal from another BSC and IO pad circuit configuration signals from control multiplexer 23.
The IO pad circuit configuration signals usually include multiple signals thus requiring complex and area consuming IO channels.
There is a growing need to provide efficient devices and methods for programming IO pad circuits.